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ADuC7060
ADC Configuration Register
Name:
Address:
Default value:
Access:
Function:
ADCCFG
0xFFFF0518
0x00
Read and write
The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs.
Table 46. ADCCFG MMR Bit Designations
Bit
7
6:5
4:3
2
1
0
Name
GNDSW_EN
ADC0ACCEN[1:0]
ADC0CMPEN[1:0]
ADC0OREN
GNDSW_RES_EN
ADCRCEN
Description
Analog ground switch enable.
This bit is set to 1 by user software to connect the external GND_SW pin to an internal analog ground
reference point. This bit can be used to connect and disconnect external circuits and components to ground
under program control and thereby minimize dc current consumption when the external circuit or
component is not being used. This bit is used in conjunction with ADCCFG[1] to select a 20 kΩ resistor to
ground.
When this bit is cleared, the analog ground switch is disconnected from the external pin.
Primary channel (32-bit) accumulator enable.
[00] = accumulator disabled and reset to 0. The accumulator must be disabled for a full ADC conversion
(ADCSTA[0] set twice) before the accumulator can be re-enabled to ensure that the accumulator is reset.
[01] = accumulator active. Positive current values are added to the accumulator total; the accumulator can
overflow if allowed to run for >65,535 conversions. Negative current values are subtracted from the
accumulator total; the accumulator is clamped to a minimum value of 0.
[10] = accumulator active. Same as [01] except there is no clamp. Positive current values are added to the
accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions. The absolute
values of negative current are subtracted from the accumulator total; the accumulator in this mode continues
to accumulate negatively, below 0.
[11] = accumulator and comparator active. This causes an ADC0 interrupt if ADCMSKI[6] is set.
Primary ADC comparator enable bit.
[00] = comparator disabled.
[01] = comparator active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADC0TH.
[10] = comparator count mode active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥
ADC0TH for the number of ADC0THC conversions. A conversion value |I| < ADC0TH resets the threshold
counter value (ADC0THV) to 0.
[11] = comparator count mode active, interrupt asserted if absolute value of ADC0 conversion result |I| ≥
ADC0TH for the number of ADC0THC conversions. A conversion value |I| < ADC0TH decrements the threshold
counter value (ADC0THV) toward 0.
ADC0 overrange enable.
Set by user to enable a coarse comparator on the primary channel ADC. If the reading is grossly (>30%
approximate) overrange for the active gain setting, then the overrange bit in the ADCSTA MMR is set. The ADC
reading must be outside this range for greater than 125 μs for the flag to be set.
Do not use this feature in ADC low power mode.
Set to 1 to enable a 20 kΩ resistor in series with the ground switch.
Clear this bit to disable this resistor.
ADC result counter enable.
Set by user to enable the result count mode. ADC interrupts occur if ADC0RCR = ADC0RCV.
Cleared to disable the result counter. ADC interrupts occur after every conversion.
Rev. 0 | Page 44 of 100
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